The present invention relates to a delay producing method applied to, for example, a DLL (Digital Locked Loop) circuit or the like mounted in a semiconductor integrated circuit or the like, and a delay adjusting method according thereto, and further relates to a delay producing circuit and a delay adjusting circuit applied with them, respectively.
A technology relating to delay production with respect to digital signals is disclosed in, for example, JP-A-2001-56723 or JP-A-2001-111394.
FIGS. 1A and 1B are diagrams for explaining a basic function of a conventional delay adjusting circuit configured by employing a delay circuit disclosed in JP-A-2001-56723. Incidentally, this delay adjusting circuit is also described in a thesis “2002 VLSI Symposium Thesis No. 9-1 A1-Gb/s/pin 512-Mb DDRII SDR AM using a digital DLL and a slew-rate-controlled output buffer; Tatsuya Matano et al.”.
This delay adjusting circuit includes first-stage to Nth stage delay elements connected in series to each other and inputted with a clock signal (CLK Input). The delay elements are shown as D1, D2, . . . , Dn, D(n+1), . . . , DN in a multi-stage structure, wherein N>n, n is a natural number no less than four, and N is a natural number no less than seven.
The clock signal is inputted (CLK Input) to an input side of the first-stage delay element D1. In this state, a delay producing circuit 10 outputs an even-stage delayed signal (Even) and an odd-stage delayed signal (Odd) by an operation of a selector S. A delay fine adjusting circuit 2 synthesizes the even-stage delayed signal and the odd-stage delayed signal and gives a fine adjustment thereto to thereby produce and output an internal clock signal (Internal CLK).
For example, FIG. 2 shows a DLL circuit wherein an initial stage circuit 3 is connected in series to an input side of a delay adjusting circuit 1, and a phase comparing circuit 4 is connected in parallel to an input side of the initial stage circuit 3 and an output side of the delay adjusting circuit 1. In this DLL circuit, assuming that the DLL is locked in one period, it is necessary that a minimum value of the total delay amount i.e., the sum of a delay amount of the initial circuit 3 and a delay amount of the delay producing circuit 10 of the delay adjusting circuit l, be no more than one period. In the foregoing thesis, the delay of the DLL circuit is set to two periods for coping with a high-speed operation. However, when the delay is large, the number of delay elements increases and a delay variation due to power supply noise becomes large which increases jitter amount. Therefore it is desirable that the DLL be locked with a delay of one period. Even if the DLL circuit is configured that the DLL is locked with a delay of two periods, when the operation is further speeded up, it is necessary to reduce the delay of the DLL circuit itself.
As a preferred example of a delay producing circuit of the delay adjusting circuit 1, the foregoing thesis describes a structure wherein an even-stage delayed signal and an odd-stage delayed signal are selected from delays of 256 stages. When the delay producing circuit is configured by using 4:1 selectors, each selector selecting one out of four inputs to output, so that delays from the 256-stage delays are selected, a hierarchical structure is obtained as schematically shown in FIG. 3. Herein the delays are grouped per four stages, and each 4:1 selector selects one from four-stage delays.
In the foregoing delay adjusting circuit, for the purpose of fully coping with an increase in operation frequency required for DLL circuits in recent years, it is necessary to increase the number of delay stages in the delay producing circuit. However, there has been a problem that when the number of delay stages increases, the number of stages (total number) of selectors also increases, and this total number of the selectors causes an operation slowdown for delay adjustment. For example, in the structure shown in FIG. 3, 256-stage delays are grouped per four stages and the 4:1 selectors are used. Although the output of the final stage is one an engineer skilled in circuit design would recognize that when 256 transistors are used for delayed output, electrical loads are added to power the selectors thereby slowing the basic operation of the DLL circuit.